Complimentary metal oxide semiconductor (CMOS) structures are the core active elements of modern electronics. Undoubtedly, the major material enabling features of Si CMOS are the superb quality of the native silicon dioxide (SiO2), Si/SiO2 interface and high crystalline perfection of the Si substrates. The field effect transistor (FET) implemented as CMOS is scalable. That is, speed and complexity improves with decreasing device feature sizes. This concept makes CMOS architecture a powerful methodology. Deep submicron room-temperature bulk Si CMOS is presently the main technology used for ultra large scale integrated circuits (ULSICs).
Because silicon is the major semiconductor material used in the semiconductor industry, silicon dioxide (SiO2) is the major insulating material used in the gate insulating layer. Silicon dioxide is a natural material that can be easily grown thermally through a steam process. Also, the silicon dioxide forms a bond with the crystalline silicon active layer that determines most of the characteristics of the FET so that it is very difficult to change the insulating material of the gate insulating layer without having deleterious effects on the FET.
Also, in the construction and design of many components it is desirable to form spaced and generally buried conductive layers in or on the substrate. These conductive layers can be used to form various components, e.g. capacitors, inductors, etc. Further, in many circuits it is desirable to form signal planes and ground planes that can be used, for example, throughout an entire integrated circuit. Also, in many FETs it is desirable to form a second, buried gate below the active channel. It has been shown that the double gate structure reduces short channel effects and parasitic capacitance in field effect transistors so that they can be scaled further (i.e. thinner and shorter channels) than bulk-Si. The buried conductive layers are useful in fabricating double gate FETs.
Clearly, one of the major problems that arises in prior art attempts to fabricate signal planes and ground planes is the formation of a buried conductive layer. In the semiconductor industry, forming a good conducting layer below, for example, crystalline or single crystal silicon is virtually unknown. One of the most common conductive buried layers includes heavily doped silicon areas, which is undesirable because free doping material has a tendency to migrate and corrupt other components, thereby shortening the life of the device and changing various characteristics (e.g. the threshold voltage). Also, heavily doped areas do not have good conductivity, thereby producing poor gate material, as well as poor signal and/or ground planes.
It would be highly advantageous, therefore, to remedy the foregoing and other deficiencies inherent in the prior art.
Accordingly, it is an object of the present invention to provide a new and improved method of fabricating one or more buried conductive layers and one or more associated insulator layers on a silicon substrate.
It is another object of the present invention to provide a new and improved structure including one or more buried conductive layers and one or more associated insulator layers on a silicon substrate.
Another object of the invention is to provide a new and improved method of fabricating signal and/or ground planes.
Another object of the invention is to provide a new and improved method of fabricating multiple box (buried oxide) layers.
A further object of the present invention is to provide new and improved buried conductive layers and insulator layers, and fabrication processes, that can be easily integrated into present day semiconductor circuits and manufacturing processes.